As semiconductor technologies advance, the manufacturing process of the flash memory also enters into the nano era. To expedite the operation of devices, increase the density of devices, and reduce the operating voltage of devices, the channel length of a gate of the device and the thickness of the oxide layer must be decreased. The gate width of the devices has been reduced from the past micro scale (10−6 m) to the present nano scale (10−9 m).
However, the miniaturization of the devices causes many problems, such as a stress-induced leakage current (SILC) and the shortened gate width causes a more serious short channel effect. To avoid the devices from being affected by the short channel effect, the thickness of the oxide layer becomes increasingly thinner. However, when the thickness of the oxide layer is reduced to 8 nm or below, the physical limitation of the materials becomes an obstacle of the device manufacturing process.
The stress-induced leakage current (SILC) is a gate leakage current increased after a constant voltage or a constant current is applied. After the thickness of the oxide layer is reduced, the stress-induced leakage current (SILC) becomes an important issue and the increase of the leakage current may cause a loss of electrons stored in a floating gate, so that the data preservation will be weakened, and the power consumption of the MOS device will be increased. In addition, the gate disturb and drain disturb of a memory bit also limit the thickness of the oxide layer significantly during the miniaturization process of the devices. Therefore, after the size of the device has reached the physical limit, there is an urgent need for overcoming the problems caused by the miniaturization of the device, in addition to the method of reducing the size of the devices.